1. Field of the Invention
The present invention relates to a reticle for manufacturing a semiconductor integrated circuit, as a mask to be used in a reduction projection exposure apparatus in a photolithography manufacturing process for a semiconductor integrated circuit device.
2. Description of the Related Art
FIG. 1 shows a reticle 300 of a conventional technique. The reticle 300 has a circuit pattern region 37 for exposing a predetermined pattern to a semiconductor chip forming portion of a semiconductor wafer, a scribing line region 38 for exposing a pattern of a cutting region for separating the semiconductor chip, and a light shielding region 39 surrounding these regions. A width of the scribing line region 38 is W/2, for example, 250 xcexcm. In the case of ⅕ reduction exposure, a width w/2 in a semiconductor wafer is 50 xcexcm.
In exposure using this reticle, as shown in FIG. 2, a shot (a region for one shot is represented by a bold line in the drawing) is performed with alignment to an outer circumference of the scribing line region. Thus, the width w/2 by the shots to adjacent portions are aligned with each other to obtain a cutting region with a width w (=100 xcexcm) in total. By the way, in FIG. 2, characters 37M and 38M are latent images for the circuit pattern region 37 and the scribing line region 38, respectively, which are formed in a resist by exposure.
However, the width of the scribing line region 38 of this reticle is W/2, and corresponds to the half width w/2 (=50 xcexcm) of a cutting region on a wafer. Thus, wafer alignment marks and TEG (test element group) patterns, which utilize the width w (=100 xcexcm) of the cutting region and have large areas cannot be formed.
FIG. 3 shows a reticle 400 of other conventional techniques. The reticle 400 has a circuit pattern region 47, a scribing line region 48, and a light shielding region 49 surrounding these regions. The width of the scribing line region 48 is W, for example, 500 xcexcm. In the case of ⅕ reduction exposure, a width w in a semiconductor wafer is 100 xcexcm, and becomes the width of the entire cutting region.
In exposure using this reticle 400, as shown in FIG. 4, each shot (a region for one shot is represented by a bold line in the drawing) is performed such that the scribing line regions are overlapped with each other. Since the width of the scribing line region 48 of this reticle has a large size W corresponding to a width w (=100 xcexcm) on a wafer, wafer alignment marks and TEG patterns, which utilize the width w of the cutting region and have large areas can be formed. By the way, in FIG. 4, characters 47M and 48M are latent images for the circuit pattern region 47 and the scribing line region 48, respectively, which are formed in a resist by exposure.
However, since double exposure is performed for the scribing line region in adjacent shots, it is necessary to form a complicated light shielding pattern in the scribing line region. This imposes a large burden in a reticle pattern arrangement design and is impractical.
Therefore, a scribing line one-side width/2 W of FIG. 1 is extended, and with this state, the scribing line width w on a wafer is extended. For, example, when w/2 is 50 xcexcm, the scribing line width w is 100 xcexcm. Also, when w/2 is 100 xcexcm, in order to form wafer alignment marks and TEG patterns, which have large areas, the scribing line width w is 200 xcexcm.
As described above, a method as shown in FIG. 4 is not used, and with the state as shown in FIG. 2 it is normally designed so that the distance between circuit patterns is extended.
However, in this case, since the scribing line width on the wafer is overextended, the number of circuit patterns which can be formed on the wafer, that is, the number of available chips decrease. Also, if the number of chips per wafer are decreased, it is necessary to spread extra wafers (increase the number of wafers) for the decreased amount, therefore the cost is increased.
To solve the above problems, a reticle as shown in FIG. 5 is disclosed in Japanese Patent Application Laid-open No. Hei 2-127641. In FIG. 5, a reticle 500 has a circuit pattern region 57, a scribing line region 58, and a light shielding region 59 surrounding these regions. The scribing line region 58 with a wide width W is coupled with the circuit pattern region 57 and located adjacent to only two end sides of the circuit pattern region 57.
According to this reticle 500, since the scribing line region 58 has a wide width W, wafer alignment patterns 55 and TEG patterns 56, which utilize the width w of the cutting region and have large areas can be formed. Also, as shown in FIG. 6, since each shot (a region for one shot is represented by a bold line in the drawing) is performed such that the scribing line regions are not overlapped with each other, it is unnecessary to form a complicated light shielding pattern in the scribing line region. Also, since a width of the scribing line region is not extended unnecessarily, the number of available chips which can be formed on a wafer are not decreased.
However, in the case of this reticle 500, alignment measurement marks (since a typical alignment measurement mark is a box mark, hereinafter explained as the box mark) 51 for overlap measurement can only be formed in end sides outside the two end sides of the circuit pattern. Thus, even if overlap against a pattern formed in before process step can be measured on a semiconductor wafer, a reticle overlap displacement of such as shot rotation and a shot magnification component cannot be measured.
By the way, in FIG. 6, characters 51M, 55M, 56M, 57M and 58M are latent images for the box marks 51, the wafer alignment patterns 55, the TEG patterns 56 the circuit pattern region 57 and the scribing line region 58, respectively, which are formed in a photoresist by exposure.
As explained above, with respect to the reticle of the conventional technique of FIG. 1, the wafer alignment marks and the TEG patterns which utilize the width w of the cutting region and have large areas cannot be formed.
With respect to the reticle of other conventional technique of FIG. 3, it is necessary to use complicated light shielding means for the scribing line region. This complicates a reticle pattern arrangement design and is impractical.
Also, in the reticle of the conventional technique of FIG. 1, when w/2 is extended, the number of chips per wafer are decreased, thereby increasing the cost by the decrease.
To solve these problems, with respect to the reticle of other conventional technique shown in FIG. 5, in which the scribing line region is located adjacent to only two end sides of the circuit pattern region, a reticle overlap displacement of shot rotation and a shot magnification component cannot be measured.
Therefore, an object of the present invention is to provide an effective reticle for manufacturing a semiconductor integrated circuit, in which a scribing line region is located adjacent to only two end sides of a circuit pattern region, which are at right angles to each other, and in which alignment measurement marks, preferably box marks for overlap measurement are formed along each of the four end sides of the circuit pattern region, so that a reticle overlap displacement of shot rotation and a shot magnification component can be measured.
According to the present invention, there is provided a reticle for manufacturing a semiconductor integrated circuit, which reticle comprises a circuit pattern region for exposing a predetermined pattern to a semiconductor chip forming portion of a semiconductor wafer and surrounded by first to fourth straight end sides thereof, a scribing line region for exposing a pattern of a cutting region for separating a semiconductor chip from the semiconductor wafer, and a light shielding region formed to surround the circuit pattern region and the scribing line region. The scribing line region is adjacent to, out of a first end side to a fourth end side of the circuit pattern region, only the first and second end sides, which are orthogonal to each other. The light shielding region is adjacent to the third and fourth end sides. The reticle of the present invention further comprises first alignment measurement marks formed at predetermined portions of the scribing line region, which face the first and second end sides, respectively, concave portions formed at predetermined portions of the light shielding region, which face the third and fourth end sides, respectively, second alignment measurement marks formed in the concave portions, respectively, and light shielding film patterns for light-shielding the portions formed, where latent images due to the second alignment measurement marks, caused by exposure shots to the adjacent portions, are formed. The first alignment measurement marks are preferably first box marks, and the second alignment measurement marks are preferably second box marks.
Here, it is preferred that the first alignment measurement marks and the second alignment measurement marks have the same shape. Also, convex portions can be formed as the light shielding film patterns in an inner circumference of the light shielding region. Further one of the second alignment measurement marks and one of the light shielding film patterns can be arranged linearly parallel to one of end sides.
Also, when a width of the scribing line region is given as W, it is preferred that the first and second alignment measurement marks are formed at portions at a distance W/2 or less from the respective end sides of the circuit pattern region, and the light shielding film patterns are formed at portions at a distance W/2 or less from an outer circumference of the scribing line region. Further, the width of the light shielding film patterns can be made equal to that of the concave portions, moreover, the shape the light shielding film patterns can be made equal to that of the concave portions.
Also, the alignment measurement marks can be formed along the respective end sides one by one. Alternatively, the alignment measurement marks can be formed along the respective end sides by plural numbers, respectively.
Further, a pattern for one semiconductor chip can be formed in the circuit pattern region. Alternatively, patterns for a plurality of semiconductor chips can be formed in the circuit pattern region.
Also, it is preferred that an alignment pattern, a TEG pattern or both of these patterns are formed in the scribing line region.